A SiC semiconductor device including a JFET having a trench structure has been known (refer to, for example, patent document 1). In the SiC semiconductor device, an N−-type drift layer, a P+-type first gate region, and an N+-type source region are formed in turn on an N+-type SiC substrate, a trench penetrating these is formed, and then an N−-type channel layer and a P+-type second gate region are formed in the trench. A gate voltage applied to a gate electrode electrically connected to the second gate region is controlled so that a drain current can flow between a source electrode electrically connected to the N+-type source region and a drain electrode electrically connected to the N+-type SiC substrate.
It can be considered that when an outer voltage-breakdown-resistant structure is formed in such a SiC semiconductor device as described above, a mesa structure is formed by forming a recess in an outer region around a transistor cell region where a JFET is formed, and then a P-type RESURF layer or a P-type guard ring layer is formed at a boundary of the recess. Although the P-type RESURF layer or the P-type guard ring layer is formed by selective ion implantation of P-type impurities after the recess is formed, the following problem occurs. This problem is described with reference to FIGS. 18A and 18B.
FIGS. 18A and 18B are cross sectional diagrams illustrating a process of forming a P-type RESURF layer as an outer voltage-breakdown-resistant structure. As shown in the drawings, a JFET basic structure is formed by forming an N−-type drift layer J2, a P+-type first gate region J3, and an N+-type source region J4 are formed in turn on an N+-type SiC substrate J1, forming a trench J5 penetrating these, and then forming an N−-type channel layer J6 and a P+-type second gate region J7 are formed in the trench J5. Then, a recess J8 deeper than the N+-type source region J3 is formed by selective etching using a mask. Then, a recess J9 deeper than the first gate region J3 is formed by selective etching using another mask. Then, a P-type RESURF layer J10 is formed by selective ion implantation of P-type impurities.
At this time, it can be considered that the P-type RESURF layer J10 can be formed by a normal ion implantation in which ion implantation of P-type impurities are performed in a direction normal to a substrate surface as shown in FIG. 18A or by an inclined ion implantation in which ion implantation of P-type impurities are performed in a direction inclined at a predetermined angle with respect to the direction normal to the substrate surface as shown in FIG. 18B.
However, when the ion implantation is performed in the direction normal to the substrate surface, the P-type RESURF layer J10 is not formed at a side surface of the recess J9 and at a corner portion that defines a boundary between the side surface and a bottom surface of the recess J9. Since the first gate region J3 and the P-type RESURF layer J10 are spaced from each other on the side surface of the recess J9, a drain breakdown voltage at the time of OFF is greatly reduced to, for example, 400V or less. That is, since the P-type RESURF layer J10 does not exist at the corner portion of the recess J9, electric field concentration occurs at this portion so that the drain breakdown voltage can be reduced.
On the other hand, when the inclined ion implantation is performed, the P-type RESURF layer J10 is formed at the side surface and the corner portion of the recess J9. Therefore, the drain breakdown voltage at the time of OFF can be increased to, for example, about 1300V. However, since there is a need to perform the inclined ion implantation in four directions in turn around the transistor cell region where the JFET is formed, an ion implantation process becomes complicated and consumes time. As a result, a manufacturing cost of the device is increased.
In the above explanation, the P-type RESURF layer J10 is formed as an outer voltage-breakdown-resistant structure. However, this is not limited to the P-type RESURF layer J10, and the same is true for when a P-type guard ring is formed.